Ultratech's advanced Laser Spike Annealing (LSA) technology enables continued device scaling and eliminates bottlenecks associated with transistor channel engineering. The main challenges regarding short channel effects include achieving maximum activation and minimal diffusion with abrupt junctions.

Ultratech's advanced annealing technology provides solutions to the difficult challenge of fabricating ultra-shallow junctions and highly activated source/drain contacts. LSA offers the flexibility to operate at near-instantaneous timeframes (micro-seconds) at temperatures up to 1350° C. At these temperatures and anneal times, nearly full activation is achieved with negligible diffusion. In addition, Ultratech's proprietary hardware design effectively minimizes the pattern density effect, reducing thermal absorption variations within a typical die to less than 2%.

Enhanced device performance [1, 2] is achieved with added activation at zero diffusion over traditional spike annealing for the sub-90 nm node. Improvement in device performance, process flexibility, best pattern uniformity, and "zero" thermal budget all make Ultratech's LSA100 Laser Spike Anneal System the intelligent choice for advanced annealing needs at 65 nm and beyond.
Key Features and Benefits:

• High dopant activation (>1E21cm -3 ) at almost "zero" thermal budget with micro-second anneal times and minimal diffusion.  Achieved < 3 nm/decade annealed implant profile abruptness
• Proven N and P-FET I_on/I_off improvements for 90 nm, 65nm and 45 nm device technologies with minimal optimization.  Customer feedback shows > 10% performance improvements in Ion/Ioff without detailed optimization
• Improvement of polysilicon depletion, reduction of > 1Å
• Localized heating minimizes wafer bow and reduces lithography misalignment
• Achieved minimal pattern density dependency effect on temperature uniformity with no changes in the device process flow - maintaining CoO advantage.  Proprietary hardware technology giving the best temperature uniformity by reducing surface thermal absorption variations to < 2%
• Process and hardware flexibility provides high throughput and wide process window for dwell time and maximum anneal temperature

In situ closed loop wafer and beam measurement metrology improves temperature uniformity and repeatability, and provides excellent diagnostic capabilities

1. A.Shima et al., "Ultrashallow Junction Formation by non-melt Laser Spike Annealing for 50-nm Gate CMOS," proceedings of VLSI 2004, Honolulu, HI, June 15-19, 2004.
2. S.K.H. Fung et al., "65nm CMOS High Speed, General Purpose and Low Power Transistor Technology for High Volume Foundry Application," proceedings of VLSI 2004, Honolulu, HI, June 15-19, 2004.
   

For additional Information on this product please Click Here